A large number of applications require the transfer of power and data through a galvanic isolation barrier with an isolation rating of several kilovolts. Such applications span several fields including industrial (e.g., high-side gate drivers), medical (e.g., implantable devices), isolated sensor interfaces and lighting. The industry standard VDE 0884-10 has been developed to expressly take into account the availability of highly integrated semiconductor isolators with micro-scale isolation barriers, either using magnetic or capacitive transfer techniques.
FIG. 1 generally illustrates these applications where a first interface and a second interface are coupled through a galvanic isolation barrier supporting both power transfer from the first interface (circuit or chip) to the second interface (circuit or chip) and bidirectional data transmission between the first and second interfaces. The first interface (circuit or chip) may, for example, be associated with a first power domain referenced to supply nodes VDD1/GND1. The second interface (circuit or chip) may, for example, be associated with a second power domain referenced to supply nodes VDD2/GND2, where VDD1 may not equal VDD2 and GND1 may not equal GND2. The galvanic isolation barrier may further address concerns with electromagnetic interference (EMI) and ground shifts. In an example implementation, the first interface may be associated with circuitry for human/data interfaces, bus/network controllers, microcontrollers (μCU), etc., while the second interface may be associated with circuitry for sensor interfaces, gate drivers, medical devices, communications networks, etc.
It is known in the art to use either post-processed or integrated isolation capacitors to perform galvanically isolated data communication. See, for example, Marwat, “Digital isolators compliance to IEC 61010-1 edition 3.0 safety requirements,” Texas Instruments, White Paper, 2014, SLYY055 (incorporated by reference). Typically, capacitive isolators use a two-chip solution (i.e., RX and TX), exploiting either RF amplitude modulation or impulsive transmission. Capacitors may be integrated with a thick isolating layer (e.g. SiO2) to achieve galvanic isolation. Isolation rating values higher than a few kilovolts may involve both technological and cost issues; and this solution may be penalizing in terms of larger area due to a lower capacitance density. Also, in certain implementations only data transfer (and not power transfer) may be achieved because capacitive isolation techniques are not well suited to power transfer due to the highly detrimental voltage partition at the input of the power rectifier. Additionally, common-mode transient (CMT) immunity (dV/dt) may become a critical factor due to high capacitive coupling.
It is also known to use transformer based isolators for data transmission. This solution is generally less sensitive to common-mode transients (CMT) when compared to isolation capacitors thanks to lower capacitive parasitics. Such isolation transformers are generally implemented by means of post-processed isolation transformers, possibly using polyimide isolation layers. Isolation rating values higher than 5 kV may be achieved with thick layers (for example, >20 microns) at the cost of a lower magnetic coupling. See, Chen, “iCoupler® products with isoPower™ technology: signal and power transfer across isolation barrier using microtransformers,” Technical Article, Analog Devices, USA, http://www.analog.com/static/imported files/overviews/isoPower.pdf (incorporated by reference).
Transfer of both data and power may be available using, for example, different transformer links. Thus, post processed isolation transformers can be exploited to transfer power with high efficiency by using a dedicated link made up of a power oscillator (i.e., the dc-ac converter) and a rectifier (i.e., the ac-dc converter). See, for example, United States Patent Application Publication No. 2010/0052630 (incorporated by reference); Chen, “Fully integrated isolated dc-dc converter using micro transformers,” Proc. IEEE Applied Power Electronics Conference and Exposition, (APEC), pp. 335-338, February 2008 (incorporated by reference); and Chen, “Isolated half-bridge gate driver with integrated high-side supply,” Proc. IEEE Power Electronics Specialists Conf. (PESC) pp. 3615-3618, June 2008 (incorporated by reference).
Examples of integrated transformers able to sustain isolation of several kilovolts have been developed. See, United States Patent Application Publication No. 2015/0364249 (incorporated by reference). Based on this technology, galvanically isolated data transfer systems are already available. See, Pulvirenti, et al., “Dispositivi con isolamento galvanico integrato”, Convegno Annuale 2014 dalla ricerca all'impresa: necessità di un trasferimento più efficace, Trieste, September 2014 (incorporated by reference). Additionally, high efficiency power transfer has been demonstrated. See, Spina, et al., “Current-reuse transformer coupled oscillators with output power combining for galvanically isolated power transfer systems,” IEEE Transaction on Circuits and Systems I, vol. 62, pp. 2940-2948, December 2015 (incorporated by reference); Lombardo, et al., “A fully-integrated half-duplex data/power transfer system with up to 40 Mbps data rate, 23 mW output power and on-chip 5 kV galvanic isolation,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, February 2016, pp. 300-301 (incorporated by reference); and Greco, et al., “A galvanically isolated dc dc converter based on current-reuse hybrid-coupled oscillators,” IEEE Trans. Circuits Syst. II, March 2016 (incorporated by reference).
The main advantages and drawbacks of the above described isolation approaches are summarized in the following table:
Isolation approachesAdvantagesDrawbacksIntegratedOn-chip galvanicTrade-off cost/area andcapacitorsisolationisolationData transferCMT additional circuitryavailablerequiredPost-processedData and power transferLow level of integrationtransformeravailableEfficiency degradationHigh CMT immunity forat high isolation ratingdata transferHigh galvanic isolationratingIntegratedOn-chip galvanicLimited isolation ratingtransformersisolationdue to oxide thicknessData transfer productsHigh CMT immunity fordata transferPower transferdemonstrated
Commercial isolated dc-dc converters typically adopt a traditional architecture that consists of: an isolated link for the power transmission (isolated power channel), which is typically made of a very high frequency (VHF) power oscillator, an isolation transformer and a power rectifier; a further isolated link for the feedback path used to control the output power (typically by means of PWM modulation of the power oscillator); and several dedicated isolated links, for example for each data channel. Of course, these architectures require at least three isolation transformers, one for the power channel, one for the feedback control channel and one for the data channel.
An alternative architecture for an isolated dc-dc converter is proposed by United States Patent Application Publication No. 2015/0180528 (incorporated by reference). FIG. 2 shows a simplified representation of this solution. FIG. 3 shows a circuit schematic. The main idea here is to use the isolated power channel also for a bidirectional (half-duplex) data communication by means of an amplitude shift keying (ASK) modulation of the power signal at the primary or the secondary windings of the isolation transformer. Proper demodulation circuitries are included to recover the data stream and clock bit stream on both the first and second interfaces.
In FIG. 3, a power oscillator apparatus includes a transformer 50 having a primary winding 51 and a secondary winding 300.
A first outgoing communications circuit 210 is coupled between the primary winding 51 and a first interface 200, and serves to encode, modulate, and prepare for transmission data across the galvanic barrier at speeds on the order of hundreds of kilobits. A first incoming communications circuit 212 is coupled between the primary winding 51 and the first interface 200, and serves to receive, demodulate, and decode data transmitted from across the galvanic barrier. The first interface 200 delivers a clock signal CLK IN and a low speed (LS) BITSTREAM to the first outgoing communications circuit 210 to be used for the transmission of the data across the galvanic barrier, and receives the clock signal CLK OUT and the high speed (HS) BITSTREAM from the first incoming communications circuit 212. It should be appreciated that the communications are half-duplex, and that the first outgoing communications circuit 210 and the first incoming communications circuit 212 are therefore not active at the same time. Also, the CLK IN and CLK OUT signals are not related.
A DC/AC converter 225 is coupled to the primary winding 51 to effectuate power transfer, and ultimately data transfer, to the secondary winding 300. An optional divider 220 is coupled between the DC/AC converter 225 and the primary winding 51, and serves to extract a reference frequency Frf to be used by the first incoming communications circuit 212 and first outgoing communications circuit 210 for decoding and encoding. The reference frequency Frf may be used by the first interface 200 in generating the clock signal CLK IN.
The first outgoing communications circuit 210 includes a first encoder 1ENC coupled to the first interface 200 to receive therefrom the bitstream LS BITSTREAM and the clock signal CLK IN, and to generate therefrom data signal to be passed to a first modulator 1MOD coupled thereto. The first modulator 1MOD receives the data signal and modulates the data signal, via amplitude modulation, such that it can be driven to the secondary winding 300 by the primary winding 51.
The first incoming communications circuit 212 includes a first demodulator 1DEMOD coupled to the primary winding 51 to receive therefrom an amplitude modulated data signal and demodulates the amplitude modulated data signal to produce a received data signal. A first decoder 1DECOD is coupled to the first demodulator 1DEMOD to receive therefrom the received data signal, and decodes the received high speed data signal and passes a resulting decoded high speed data signal HS BITSTREAM to the first interface 200 together with the clock signal CLK OUT.
An AC/DC converter 70, such as a rectifier/regulator is coupled to the secondary winding 300 and is powered by the power transferred from the DC/AC converter 225, across the galvanic barrier, via the primary winding 51. The AC/DC converter 70 outputs an isolated voltage supply to the second interface 202.
A second outgoing communications circuit 214 is coupled between a second interface 202 and the secondary winding 300, and serves to encode, modulate, and prepare the data for transmission across the galvanic barrier at speeds on the order of tens of megabits. A second incoming communications circuit 216 is coupled between the second interface 202 and the secondary winding 300, and serves to receive, demodulate, and decode the data transmitted across the galvanic barrier. The second interface 202 delivers the clock signal and the bitstream to the second outgoing communications circuit 214 to be used for the transmission of the data across the galvanic barrier, and receives the clock signal and the data from the second outgoing communications circuit 214.
The second outgoing communications circuit 214 includes a second encoder 2ENC coupled to the second interface 202 to receive therefrom the bitstream HS BITSTREAM and a clock signal CLK IN, and generates therefrom a data signal. A second modulator 2MOD is coupled to the second encoder 2ENC to receive therefrom the data signal and modulates the data signal, via amplitude modulation, into a modulated data signal to be driven to the secondary winding 300 for transmission across the galvanic barrier.
The second incoming communications circuit 216 includes a second demodulator 2DEMOD coupled to the secondary winding 300 to receive therefrom an amplitude modulated data signal and demodulates the amplitude modulated data signal to produce a received data signal. A second decoder 2DECOD is coupled to the second demodulator 2DEMOD to receive therefrom the received data signal, and decodes the received data signal into a decoded data signal to be passed to the second interface 202.
An optional divider 221 is coupled between the secondary winding 300 and the second interface 202, and serves to extract a reference frequency Frf to be used by the second incoming communications circuit 216 and second outgoing communications circuit 214 for decoding and encoding.
The system in FIG. 3 is a general scheme that can be used in different application fields. Typically, interface 200 is a microcontroller, while interface 202 is an isolated front-end e.g., isolated RS-485 transceivers, isolated CAN transceivers, isolated RS-232 transceivers, isolated I2C transceivers, isolated ADC, isolated USB transceivers, etc.
The circuits described above with reference to FIG. 3 allow the transfer of power and data across a galvanic barrier using the same transformer. This reduces the complexity and cost as compared to other prior art circuits. Unfortunately, the foregoing approach presents several drawbacks as follows:
Variable power functionality is not compatible with data transmission: Data communication requires the presence of the power signal and this is not compatible with typical power control that exploits an on/off modulation (i.e., PWM modulation) of the power oscillator to preserve efficiency. Therefore, this solution cannot be used when a variable/controlled output power is required. Moreover, it also needs an output voltage regulator.
Maximum data bitrate is limited by the ratio of carrier frequency to data rate: Since data transmission is implemented as modulation of the power signal, the maximum bit rate is limited by the ratio of power signal frequency (i.e., carrier frequency) and data signal frequency. The power signal frequency is the result of a design tradeoff to maximize system efficiency and therefore cannot be increased to improve the data rate. As a consequence, at high data rates, the demodulation is critical and requires customized demodulation circuitry.
The architecture is not suited to high power applications (i.e., the power level is limited to a few tens of milliWatts) due to contrasting specs on the transformer size (power vs. CMT immunity): Higher power applications require larger isolation power transformers and hence there are higher parasitic capacitances between primary and secondary windings of the isolation transformer. This limits the CMT immunity performance of the data transmission channel, since injected current due to CMTs are proportional to parasitic primary-to-secondary capacitances (i.e. I=C dV/dt). Therefore, the architecture can be used only at low power levels with small isolation transformers.
Data transmission significantly affects the overall power efficiency: Since data transmission is obtained as ASK modulation of the power signal, communication affects the overall output power level and power efficiency, especially if a high modulation index is used to improve system robustness in terms of bit error rate (BER).